罗必露,黄琦,曹瓅月,李坚,井实.基于FPGA的全场景试验系统主时钟终端频率校准方法[J].电测与仪表,2015,52(19):. LUO Bi-lu,HUANG Qi,CAO Li-yue,LI Jian,JING Shi.Frequency Correction of Master clock terminal for Whole-view Test System based on FPGA[J].Electrical Measurement & Instrumentation,2015,52(19):.
基于FPGA的全场景试验系统主时钟终端频率校准方法
Frequency Correction of Master clock terminal for Whole-view Test System based on FPGA
Aiming at the problem of low accuracy and insufficient stability of frequency of Master clock terminal of Whole-view Test System, the paper presents a simple and effective method to Correct frequency of OCXO (oven controlled crystal oscillator). The method bases on the principle of establishing time system within FPGA(Field Programmable Gata Array). Measure the periodic deviation between OCXO and GPS through TDC (Time to Digital Converter) .Modify the value of period within FPGA, reaching the purpose of frequency correction. To reduce the impact of GPS signal jitter, using the moving average filter algorithm to tame OCXO quickly. Through simulation and experimental trials the clock frequency accuracy is higher than the average 5×10-10, and the time accuracy is better than 1.8μ/h, after OCXO was tamed.
