基于Nand Flash 的BCH校验方法设计与实现

单彦虎; 武慧军; 焦新泉; 秦菲

单彦虎,武慧军,焦新泉,秦菲.基于Nand Flash 的BCH校验方法设计与实现[J].电测与仪表,2017,54(22):.
shanyanhu,wuhuijun,jiaoxinquan,qinfei.Design and Implementation of BCH verification Method Based on Nand Flash[J].Electrical Measurement & Instrumentation,2017,54(22):.

基于Nand Flash 的BCH校验方法设计与实现

Design and Implementation of BCH verification Method Based on Nand Flash

DOI：

中文关键词: BCH校验并行编码分块译码 FPGA 可靠性

英文关键词:BCH checking, parallel coding, block decoding, FPGA, reliability

基金项目:

作者中文名	作者英文名	单位
单彦虎	shanyanhu	中北大学
武慧军	wuhuijun	中北大学
焦新泉	jiaoxinquan	中北大学
秦菲	qinfei	中北大学

摘要点击次数: 1965

中文摘要:

针对传统汉明码ECC校验方法纠错能力差的特点,结合Nand Flash 闪存内部组织结构,提出一种(4200,4096,8)的BCH码ECC校验方法。该方法采用并行编码方式,且对占用逻辑资源最多的译码器部分采用并行流水线分块译码,极大的提升了编译码效率。以FPGA为验证平台,通过大量数据读写表明,该方法大大提高了存储可靠性,为目前大容量存储提供了参考,具有较高的实用价值。

英文摘要:

According to the internal structure of the nand flash memory and poor correct capability of traditional ECC of Hamming checking method, a kind of (4200,4096,8)BCH code for ECC verification is proposed. Parallel coding mode is chosen in this method. What’s more, parallel pipeline block decoding method is used for the decoder, which occupied most logical resource. With the method above, decoding efficiency is greatly increased. FPGA is selected as the verification platform, verification on this platform shows that the storage reliability is most significantly improved using BCH code for ECC verification. The proposed method has high practical value and reference for current large capacity storage is provided.

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