Line Phase-locked Loop has poor stability and weak anti-interference ability in the application of high frequency, so the application is limited. All digital phase-locked loop has not these problems, the design of a digital PLL for high frequency applications is necessary. Analysis the principle of Flip-Flop all digital phase-locked loop and build S domain mathematical modeling. Analysis the global stability, dynamic response of the phase-locked loop by this model and build the parameter constraints relation. Design a kind of all-digital phase-locked loop by Xilinx ISim simulation and FPGA implementation, the results show that this all-digital phase-locked loop has a wide frequency range, fast dynamic response, small steady-state error and certain application value.
