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文章摘要
一种CIGRE直流输电标准模型锁相环的改进方法
One Improved Method of Phase-locked Loop of CIGRE HVDC Benchmark Model
Received:June 24, 2014  Revised:June 24, 2014
DOI:
中文关键词: 高压直流输电  锁相环  前置滤波  触发脉冲  不对称故障
英文关键词: HVDC  Transmission, Phase-locked  Loop, prefilter, trigger  pulse, asymmetric  fault
基金项目:国家自然科学(51267017);自治区重大攻关项目(201230115-3);教育部创新团队项目(IRT1285)
Author NameAffiliationE-mail
LIU Jun-yong* Engineering Research Center For Renewable Energy Power Generation&Grid Technology approved by Education Ministry for its establishment under College of Electrical Engineering Xinjiang University 289469518@qq.com 
WANG Wei-qing Engineering Research Center For Renewable Energy Power Generation&Grid Technology approved by Education Ministry for its establishment under College of Electrical Engineering Xinjiang University  
WANG Hai-yun Engineering Research Center For Renewable Energy Power Generation&Grid Technology approved by Education Ministry for its establishment under College of Electrical Engineering Xinjiang University  
LI Jian Engineering Research Center For Renewable Energy Power Generation&Grid Technology approved by Education Ministry for its establishment under College of Electrical Engineering Xinjiang University  
SHI Guang Engineering Research Center For Renewable Energy Power Generation&Grid Technology approved by Education Ministry for its establishment under College of Electrical Engineering Xinjiang University  
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中文摘要:
      为了实时追踪换相电压的相位变化,提高高压直流输电(HVDC)系统中换流器脉冲触发装置的控制精度,本文提出了一种改进的锁相环(PLL)同步倍频技术。基于PSCAD传统直流输电模型,在原脉冲触发控制装置的基础上改进了锁相环,并通过一种特殊的前置滤波技术,滤除故障时换相线电压的谐波和噪声,使之作为锁相环的输入信号。在交流系统发生不对称故障导致换流器换相电压过零点偏移的情况下,应用本文提出的方法,通过CIGRE提出的HVDC第一标准模型进行仿真验证,得出所搭建的模型完全能满足特高压直流输电系统极控制层对等间隔触发脉冲的要求。
英文摘要:
      In order toS track phaseSchange of commutationSvoltage and improve the controlSprecision ofShigh voltage direct current transmissionS(HVDC)S pulse triggeringSdevice, this paper put forward an improved synchronousSfrequency doubling technology inSSphase-locked loop. Based on the PSCAD traditionalSDC transmissionSmodel, improvedSPLL in the foundation of the originalSpulse triggerScontrolSdevice, and throughSa specialSpre filteringStechnique, filter the harmonic and noiseSofScommutation line-voltagesSduring faults, and make it as the input signalSof PLL. In the commutationSvoltage overSzero offset case caused by asymmetric fault in theSACSsystem, to apply this method proposed by this paper, through the HVDC first benchmark modeSproposed by CIGRE toSsimulate and verify, this model can meet the requirement of equal intervalStrigger pulse of HVDCStransmission system polar control level completely.
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