• HOME
  • About Journal
    • Historical evolution
    • Journal Honors
  • Editorial Board
    • Members of Committee
    • Director of the Committee
    • President and Editor in chief
  • Submission Guide
    • Instructions for Authors
    • Manuscript Processing Flow
    • Model Text
    • Procedures for Submission
  • Academic Influence
  • Open Access
  • Ethics&Policies
    • Publication Ethics Statement
    • Peer Review Process
    • Academic Misconduct Identification and Treatment
    • Advertising and Marketing
    • Correction and Retraction
    • Conflict of Interest
    • Authorship & Copyright
  • Contact Us
  • Chinese
Site search        
文章摘要
基于FPGA的全场景试验系统主时钟终端频率校准方法
Frequency Correction of Master clock terminal for Whole-view Test System based on FPGA
Received:July 25, 2014  Revised:July 25, 2014
DOI:
中文关键词: 时间数字转换器  FPGA  周期计数值  恒温晶振
英文关键词: time  to digital  converter, Field  Programmable Gata  Array ,oven  controlled crystal  oscillator,period  counter
基金项目:
Author NameAffiliationE-mail
LUO Bi-lu* University of Electronic science and Technology of China 241305534@qq.com 
HUANG Qi University of Electronic science and Technology of China  
CAO Li-yue University of Electronic science and Technology of China  
LI Jian University of Electronic science and Technology of China  
JING Shi University of Electronic science and Technology of China  
Hits: 2324
Download times: 883
中文摘要:
      针对全场景试验系统主时钟终端的时钟源频率精度低和稳定性不足的问题,本文提出了一种简单有效的恒温晶振校准方法。该方法基于FPGA时间系统建立的原理,通过TDC(时间数字转换器)测得的恒温晶振与GPS秒脉冲之间的周期偏差值,修改FPGA内部计数器的周期计数值,达到校准主时钟频率的目的。为降低GPS信号抖动的影响,采用滑动平均滤波算法,实现恒温晶振的快速驯服。通过仿真和试验测试,驯服后主时钟平均频率精度高于5×10-10,守时精度优于1.8μ/h。
英文摘要:
      Aiming at the problem of low accuracy and insufficient stability of frequency of Master clock terminal of Whole-view Test System, the paper presents a simple and effective method to Correct frequency of OCXO (oven controlled crystal oscillator). The method bases on the principle of establishing time system within FPGA(Field Programmable Gata Array). Measure the periodic deviation between OCXO and GPS through TDC (Time to Digital Converter) .Modify the value of period within FPGA, reaching the purpose of frequency correction. To reduce the impact of GPS signal jitter, using the moving average filter algorithm to tame OCXO quickly. Through simulation and experimental trials the clock frequency accuracy is higher than the average 5×10-10, and the time accuracy is better than 1.8μ/h, after OCXO was tamed.
View Full Text   View/Add Comment  Download reader
Close
  • Home
  • About Journal
    • Historical evolution
    • Journal Honors
  • Editorial Board
    • Members of Committee
    • Director of the Committee
    • President and Editor in chief
  • Submission Guide
    • Instructions for Authors
    • Manuscript Processing Flow
    • Model Text
    • Procedures for Submission
  • Academic Influence
  • Open Access
  • Ethics&Policies
    • Publication Ethics Statement
    • Peer Review Process
    • Academic Misconduct Identification and Treatment
    • Advertising and Marketing
    • Correction and Retraction
    • Conflict of Interest
    • Authorship & Copyright
  • Contact Us
  • 中文页面
Address: No.2000, Chuangxin Road, Songbei District, Harbin, China    Zip code: 150028
E-mail: dcyb@vip.163.com    Telephone: 0451-86611021
© 2012 Electrical Measurement & Instrumentation
黑ICP备11006624号-1
Support:Beijing Qinyun Technology Development Co., Ltd