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文章摘要
基于FPGA的CRC查表法设计及优化
Based on the FPGA design and optimization of CRC look-up table method
Received:November 07, 2015  Revised:November 07, 2015
DOI:
中文关键词: CRC校验  串行通信  FPGA  查表法  VHDL
英文关键词: CRC check  Serial communication  FPGA  Look-up table method  VHDL
基金项目:
Author NameAffiliationE-mail
Xia Zhonghai* State key laboratory of electronic testing technology of North university of china,Shanxi taiyuan hai7029@163.com 
yong-feng ren State key laboratory of electronic testing technology of North university of china,Shanxi taiyuan renyongfeng@nuc.edu 
Jia Xingzhong State key laboratory of electronic testing technology of North university of china,Shanxi taiyuan 18636687318@162.com 
Guo Jiaxin State key laboratory of electronic testing technology of North university of china,Shanxi taiyuan 137688171@qq.com 
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中文摘要:
      循环冗余校验Cyclic Redundancy Checks(CRC)具有检错能力极强,开销小,易于用编码器及检测电路实现,远远优于奇偶校验及算术和校验等方式的特点,故在串行通信中添加CRC校验可保证通信的有效性。而FPGA具有灵活稳定,快速高效的特点,故用VHDL实现CRC查表法设计并对其优化分析,使其在串行通信中具有良好的稳定性,提高数据传输的准确性。
英文摘要:
      Cyclic Redundancy check (CRC) has the strong ability of error detection, overhead is small, easy to use the encoder and the realization of detection circuit, is much better than the parity and arithmetic and calibration method, the characteristics of the CRC check is added in the serial communication can ensure the effectiveness of communication. And the FPGA with flexible and stable, rapid and efficient characteristics, so the design with VHDL realization of CRC look-up table method and the optimization analysis, make its have good stability in serial communication, improve the accuracy of the data transmission.
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