At present, the development of high-speed serial JESD204B interface is difficult to get rid of foreign restrictions and lack of independent design technical experience. In order to promote the localization process of JESD204B interface, this paper introduces a high-speed sampling data analysis and receiving circuit based on the JESD204B protocol. The physical layer of JESD204B interface is achieved by Xilinx high-speed serial transceiver GTX, which used 8b/10b decoder within the GTX to decode serial data stream, and aligned byte according to the 4 byte alignment. So configuration and the function of the GTX port signal is studied. The link layer of the interface is completed through the FPGA logic design, adopting modular design thinking, a synchronous request management module is designed, which completed link initialization through the judgment receives the identifier of the number of consecutive, and the receive data processing module is designed to detect and replace the data frame tail control byte. After testing and verification, the interface can correctly analyze data at 7.4 Gbps transmission rate, and the design interface circuit meets engineering application requirements.