针对SRAM存储器存在的软错误（Soft error），本文提出了一种可应用于差集码（Difference Set Code, DS）的奇数大数逻辑门（Majority Logic Gate，MLG）电路。本文构造的θ（θ为奇数）输入的MLG电路需要1个(θ+1)/2输入的排序网络、1个 (θ-1)/2输入的排序网络、(θ-1)/2个2输入与门、1个(θ+1)/2输入或门。在FPGA上对比使用传统MLG电路和本文构造的MLG电路实现DS码译码器的硬件开销。结果表明，相比于使用传统MLG电路，DS码译码器在使用本文构造的MLG电路时，有效降低了Slices、逻辑延时、6-LUT、Flip-Flops。
英文摘要:
Aiming at the soft errors in SRAM memory, an odd-input majority logic gate (MLG) circuitry that can be applied to difference set code (DS) is proposed. When The θ is odd, the θ-input MLG circuitry consists of one (θ+1)/2-input sorting network, one (θ-1)/2-input sorting network, (θ-1)/2 2-input AND-gate, one (θ+1)/2-input OR-gate. The hardware overhead of DS decoder is compared between the traditional MLG circuitry and the proposed MLG circuitry on FPGA. Compared with the traditional MLG circuit, when the DS decoder uses the proposed MLG circuitry, Slices, logic delay, 6-LUT, Flip-Flops are reduced.