In a broadband low voltage power line channel, the interference from channel noise is heavy and results in a poor communication performance. This paper presents a optimization methods of the decoder of LDPC code for power line communication system, and implementation through FPGA. The correction process ofthis algorithm just includes simple arithmetic and logic operations, which is easy to be implemented by FPGA. Experiment has proved, compared with usual partial parallel decode structure, structure provided by this paper saves much hardware resources. Software and hardware simulations show that the proposed scheme approaches to the performance of a floating-point calculation based the BP algorithm. Therefore, it can be widely used in power line communications and so on with low signal-to-noise ratio transmission.