• HOME
  • About Journal
    • Historical evolution
    • Journal Honors
  • Editorial Board
    • Members of Committee
    • Director of the Committee
    • President and Editor in chief
  • Submission Guide
    • Instructions for Authors
    • Manuscript Processing Flow
    • Model Text
    • Procedures for Submission
  • Academic Influence
  • Open Access
  • Ethics&Policies
    • Publication Ethics Statement
    • Peer Review Process
    • Academic Misconduct Identification and Treatment
    • Advertising and Marketing
    • Correction and Retraction
    • Conflict of Interest
    • Authorship & Copyright
  • Contact Us
  • Chinese
Site search        
文章摘要
模拟量输入合并单元暂态时间特性测试技术研究
Technology of ECT transmission delay testing in transient state
Received:May 19, 2014  Revised:May 19, 2014
DOI:
中文关键词: 模拟量输入合并单元,暂态时间特性,突变量检测,相位补偿修正,DPLL,复合误差
英文关键词: Electronic  current transformer, Transient  transmission delay, Mutation  detection, Phase  compensation, FPGA
基金项目:
Author NameAffiliationE-mail
Shu Zhan State Grid Jiangxi Electric Power Research Institute,Nan Chang shuzhan2003@126.com 
Tang Han-song* Jiangsu LingChuang Electric Automation Co,Ltd xsunson@163.com 
Xie Guo-qiang State Grid Jiangxi Electric Power Research Institute,Nan Chang  
Liu Jian State Grid Jiangxi Electric Power Research Institute,Nan Chang  
Hits: 2133
Download times: 884
中文摘要:
      本文介绍了模拟量输入合并单元的暂态延时与稳态延时之间的差异性,并从继电保护应用的角度关注了模拟量输入合并单元暂态下的传变延时问题,阐述了暂态延时与稳态延时的差异性以及在工程中测试的必要性,提出了一种基于基于精确离散时间控制的的合并单元暂态时间特性测试方案,采用数字相位锁定器(DPLL)消除数字量时序抖动,利用突变量检测确定初始时刻,再结合相位提取进行时差补偿修正,很好的消除了测试中的各个误差因素,利用同步信号异常、报文离散度变化等突发事件作为触发条件,测试这些异常过程时间特性的变化对电流电压复合误差的影响。通过开发的测试系统在工程中的应用,以验证本本时间特性测试技术方案的可行性。
英文摘要:
      Study on the electronic current transformer transient transmission delay problem from the application of relay protection angle. Explain the difference between transient delay time and steady state delay time, as well as the necessity test in engineering. Proposed a test scheme based on simulation sampling with high accuracy and high bandwidth, and the precise time scale digital calibration receiver. Using the digital phase locked loop (DPLL) to eliminate the digital timing jitter. Using mutation detecting to determine the initial time, combined with the phase extraction for time delay compensation. The various error factors have been eliminated in the test well. Through the application of the developed test system in engineering, proved the feasibility of the scheme.
View Full Text   View/Add Comment  Download reader
Close
  • Home
  • About Journal
    • Historical evolution
    • Journal Honors
  • Editorial Board
    • Members of Committee
    • Director of the Committee
    • President and Editor in chief
  • Submission Guide
    • Instructions for Authors
    • Manuscript Processing Flow
    • Model Text
    • Procedures for Submission
  • Academic Influence
  • Open Access
  • Ethics&Policies
    • Publication Ethics Statement
    • Peer Review Process
    • Academic Misconduct Identification and Treatment
    • Advertising and Marketing
    • Correction and Retraction
    • Conflict of Interest
    • Authorship & Copyright
  • Contact Us
  • 中文页面
Address: No.2000, Chuangxin Road, Songbei District, Harbin, China    Zip code: 150028
E-mail: dcyb@vip.163.com    Telephone: 0451-86611021
© 2012 Electrical Measurement & Instrumentation
黑ICP备11006624号-1
Support:Beijing Qinyun Technology Development Co., Ltd